Novel Vantage- Scalable cache Compression Scheme

In today’s world speed is one of the important factor that is considered for selecting any electronic component in the market. Speed of a microprocessor based system mainly depends on the speed of the microprocessor which in turn depends on the memory access time. cache compression is one of the way to increase speed of a microprocessor based system since it increases cache capacity and off-chip bandwidth. Storing compressed lines in the cache increases the effective cache capacity. For example, a compressed L1 cache design where each set can store either one uncompressed line or two compressed lines. Increasing the effective cache size can eliminate misses and thereby reduce the time lost to long off-chip miss penalties. However, compression increases the cache hit time, since the decompression overhead lies on the critical access path. Depending upon the balance between hits and misses, cache compression has the potential to either greatly help or greatly hurt performance.